1. Technical Field
The present invention relates to a method for rendering graphics and a graphics rendering engine, and more particularly, to a method and apparatus for reducing a memory bandwidth by rapidly removing an invisible fragment via a depth filter in a three-dimensional (3D) space in a 3D graphics rendering engine.
2. Discussion of the Related Art
Generally, high-performance 3D rendering processors support interpolation, texture mapping, per-fragment operations, depth tests (also called Z-tests), etc.
In particular, texture mapping plays a key role in estimating the performance of 3D rendering processors. To support such texture mapping, large-scale hardware and high-capacity memory devices are required. In this sense, memory bandwidth is a factor in designing 3D rendering processors. In addition, the texture mapping's performance efficiency is a factor in designing 3D rendering processors.
To solve memory bandwidth-related problems in 3D graphics rendering engines, 3D graphics hardware manufacturers such as, ATI Technologies Inc. and NVIDIA® Corporation have suggested employing the Hyper-Z architecture and Light-speed Memory Architecture (LMA), respectively.
Since the Hyper-Z architecture and LMA require a 24-bit or 32-bit storage space for each fragment, an on-chip memory having a high-capacity storage space is necessary to implement the Hyper-Z architecture or LMA.